Luke Demoracski, Ph.D.

Luke Demoracski, Ph.D.

Attorney

t:
617-443-9292, ext 276
f:
617-443-0004
e:
ldemoracski@sunsteinlaw.com
Worcester Polytechnic Institute
B.S. Electrical Engineering, computer engineering, Honors
Northeastern University
M.S. Electrical Engineering
Northeastern University

Ph.D. Electrical Engineering, Computer Engineering

Suffolk University School of Law
J.D., Dean’s List

Practice Areas

Education

  • Worcester Polytechnic Institute B.S. Electrical Engineering, computer engineering, Honors
  • Northeastern University M.S. Electrical Engineering
  • Northeastern University

    Ph.D. Electrical Engineering, Computer Engineering

  • Suffolk University School of Law J.D., Dean’s List

Profile

Luke is a patent attorney with over seven years of patent preparation and prosecution experience that spans a wide range of technologies. Luke also has over sixteen years of engineering experience that includes hardware and software development for various technologies. Prior to entering the field of law, Luke worked as an engineer at start-up companies and large companies.

Experience

  • Dr. Demoracski has determined the patentability of inventions for diverse technologies including automated speech recognition, natural language processing, computer systems, computer-aided design, multi-dimensional modeling and simulation, cybersecurity, software engineering, educational software, databases, user interfaces, search engines, computer storage systems, electrical engineering, electronics, semiconductors, circuitry, analog design, digital design, parallel processing, printed circuit boards, medical devices, mechanical engineering, mechanical devices, audio speakers, manufacturing processes and devices, process engineering, image processing, autonomous vehicles, optics, computer networking protocols, network processors, network equipment, videoconferencing, sensor networks, sensor systems including sonar and LIDAR, mobile networks, wired and wireless networks, and telecommunications.
  • Assisted clients with patent portfolio development/review including invention data mining with clients and inventors.
  • Managed international families of patent applications.
  • Drafted U.S. and PCT patent applications, conducted invention disclosures, performed and reviewed patentability searches.
  • Prosecuted patent applications at the United States Patent and Trademark Office, including drafted responses to Office Actions, conducted Examiner Interviews, managed filings of application documents including Information Disclosure Statements, Terminal Disclaimers, Assignments, Declarations, and other necessary filing documents.
  • Worked with foreign associates in the prosecution of foreign applications.
  • As an engineer, performed hardware and software development that included ASIC, FPGA, Board and System Design and Verification, ATM, ATE, Computer Systems, Wired and Wireless Networks, Fault Tolerance, Networking Protocols: ATM, IP, TCP, BVR, 802.1X, SONET, and several software and hardware languages.
  • Performed self-funded research resulting in eleven technical publications and award of a Ph.D. degree. Research included fault tolerant wireless networking, hardware-software co-design, hardware verification, and DNA computing.

Professional and Community Involvement

Boston Patent Law Association, IEEE Senior Member, Tau Beta Pi, Eta Kappa Nu, IEEE Local Chair for NCA Symposium, IEEE Boston Entrepreneur’s Network, manuscript reviewer: various IEEE transactions journals

Select Publications and Presentations

  1. Fault-Tolerant Beacon Vector Routing for Mobile Ad Hoc Networks, IEEE International Parallel and Distributed Processing Symposium, April 2005, Denver, CO.
  2. An Approach Functional Decomposition Applied to State-Based Designs, IEEE Rapid System Prototyping Workshop, June 2005, Montreal, Canada.
  3. Framework for Improved Partitioning and Automatic Task Graph Extraction for State-Based Designs, International Workshop on Logic Synthesis, June 2005, San Diego, CA.
  4. Design Verification with 0-In Assertions: A Case Study, First Annual Teradyne Technical Conference, June 2005, Boston, MA.
  5. Cluster-Based Load-Balanced Fault-Tolerant Beacon Vector Routing for Wireless Sensor Networks, IEEE Dependable Systems and Networks Conference, July 2005, Yokohama, Japan.
  6. Power Consumption Comparison for Regular Wireless Topologies using Fault-Tolerant Beacon Vector Routing, IEEE International Parallel and Distributed Processing Symposium, April 2005, Greece.
  7. A Scalable Framework for Defect Isolation of DNA Self-assembled Networks, The 22nd IEEE International. Symposium on Defect and Fault Tolerance in VLSI Systems, September 2007, Rome, Italy.

Bar and Court Admissions

Massachusetts

U.S. Patent & Trademark Office

U.S. District Court for the District of Massachusetts

Practice areas

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